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IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS OCTAL TRANSPARENT LATCH
IDT74FCT2373AT/CT
FEATURES:
* * * * A and C grades Low input and output leakage 1A (max.) CMOS power levels True TTL input and output compatibility: - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) Meets or exceeds JEDEC standard 18 specifications Resistor outputs -15mA IOH, 12mA IOL Reduced system switching noise Available in QSOP package
DESCRIPTION:
The FCT2373T is an octal transparent latch built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is high. When LE is low, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is low. When OE is high, the bus output is in the high-impedance state. The FCT2373T has balanced drive outputs with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. The FCT2373T parts are plug-in replacements for FCT373T parts.
* * * *
FUNCTIONAL BLOCK DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D O G
D O G
D O G
D O G
D O G
D O G
D O G
D O G
LE
OE O0 O1 O2 O3 O4 O5 O6 O7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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JUNE 2006
DSC-5497/6
(c) 2006 Integrated Device Technology, Inc.
IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to +7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA VTERM(3) TSTG IOUT
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
QSOP TOP VIEW
VCC O7 D7 D6 O6 O5 D5 D4 O4 LE
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF
NOTE: 1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names Dx LE OE Ox Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) 3-State Outputs Description
FUNCTION TABLE(1)
Dx L H X Inputs LE H H X OE L L H Outputs Ox L H Z
NOTE: 1. H = HIGH Voltage Level X = Don't Care L = LOW Voltage Level Z = High Impedance
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IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 5%
Symbol VIH VIL IIH IIL IOZH IOZL II VIK VH ICC Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) High Impedance Output Current (3-State Output Pins)(4) Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = Max. VIN = GND or VCC VCC = Max., VI = VCC (Max.) VCC = Min., IIN = -18mA -- Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max. VI = 2.7V VI = 0.5V VI = 2.7V VI = 0.5V Min. 2 -- -- -- -- -- -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -0.7 200 0.01 Max. -- 0.8 1 1 1 1 1 -1.2 -- 1 A V mV mA Unit V V A A A
OUTPUT DRIVE CHARACTERISTICS
Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3) VCC = Min IOH = -15mA VIN = VIH or VIL VCC = Min IOL = 12mA VIN = VIH or VIL Min. 16 -16 2.4 -- Typ.(2) 48 -48 3.3 0.3 Max. -- -- -- 0.5 Unit mA mA V V
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C.
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IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = GND One Input Toggling 50% Duty Cycle IC Total Power Supply Current(6) VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle OE = GND LE = Vcc One BitToggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle OE = GND LE = Vcc Eight Bits Toggling
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2+ fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz.
Test Conditions(1)
Min. --
Typ.(2) 0.5 0.06
Max. 2 0.12
Unit mA mA/ MHz
VIN = VCC VIN = GND
--
VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
0.6
2.2
mA
--
0.9
3.2
VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
1.2
3.4(5)
--
3.2
11.4(5)
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IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1)
74FCT2373AT Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW Set-up Time HIGH or LOW, Dx to LE Hold Time HIGH or LOW, Dx to LE LE Pulse Width HIGH(3) 2 1.5 5 -- -- -- 2 1.5 5 -- -- -- ns ns ns Output Disable Time 1.5 5.5 1.5 5 ns Parameter Propagation Delay Dx to Ox Propagation Delay LE to Ox Output Enable Time 1.5 6.5 1.5 5.5 ns Condition(1) CL = 50 pF RL = 500 2 8.5 2 5.5 ns Min.(2) 1.5 Max. 5.2 74FCT2373CT Min.(2) 1.5 Max. 4.2 Unit ns
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested.
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IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 500W VIN Pulse Generator RT D.U.T . VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low Switch Closed Open
50pF CL
500W
All Other Tests
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal Link
Test Circuits for All Outputs
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC.
tSU
tH
tREM
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
Octal Link
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
1.5V
tSU
tH
Pulse Width
Octal Link
Set-Up, Hold, and Release Times
ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 3.5V 1.5V tPHZ
DISABLE 3V 1.5V tPLZ 0V 3.5V 0.3V 0.3V VOL VOH 0V
Octal Link
Octal Link
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
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IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
XXXX IDT XX FCT Device Type Temp. Range XX Package
Q QG
Quarter-size Small Outline Package QSOP - Green
2373AT Octal Transparent Latch 2373CT
74
- 40C to +85C
CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com
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for Tech Support: logichelp@idt.com

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